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L6237 5v spindle motor driver product preview operates from 5v supply 1.5a maximum start-up current integrated phases commutation se- quencer programmable slew rate back emf comparator output brake function input with user con- figurable delay low power consumption mode over temperature protection description the L6237 is a triple half bridge driver intended for use in brushless dc motor applications. the device is designed to drive a three phase, brushless dc motor, typically used in rigid disk drives. power drivers are fabricated in dmos technology and feature fast internal recircula- tion diodes. all logic inputs are cmos/ttl com- patible, and an internal transconductance loop is included for linear motor speed control. upper n- channel dmos transistors are driven via an in- ternal step-up converter. the ic will be manu- factured in a plastic tqfp64 surface mount package. this is advanced information on a new product now in development or undergoing evaluation. details are subject to change without notice. september 1993 block diagram tqfp64l 1/11
pin connection (top view) absolute maximum ratings symbol parameter value unit v ds(sus) output sustaining voltage 14 v v p supply voltage 7 v v i logic input voltage range -0.3 to v p v v in transconductance loop input voltage range -0.3 to vp v i peak peak current (pulsed: t on = 5ms; d.c. = 10%) tj = 25 c 2.0 a t jmax maximum junction temperature 145 c i max maximum current (d.c.) 1.2 a ptot total power dissipation at t amb =70 c 0.85 w t amb operating ambient temperature -0 to 70 c t stg storage temperature -40 to 150 c thermal data symbol parameter value unit r th j-amb thermal resistance junction-ambient (*) 90 c/w (*) mounted on board with minimized copper area. L6237 2/11
pin functions n. name function 1, 2, 9, 11, 12, 15, 16, 17, 18, 24, 25, 31, 32, 33, 34, 44, 47, 48, 49, 50, 56, 57, 63, 64 n.c. not connected. 3, 4, 13, 14 out b the outputs of the three dmos half bridge drivers. 26, 27 out c 54, 55 out a 5 mux_sgl logic input used to configure bemf output to be multiplexed (high) or a single output (low). 6, 7, 8, 39, 40, 41, 42 gnd ground. 10 v dd power supply for internal circuitry. 5v power supply must be connected directly to pin. 19 fref used as time reference for internal period and mask counters. 20 bemf output for bemf comparator. 21 ctap input for center tap of motor. 22, 23, 45, 46 vp 5v power supply for the dmos drivers. series schottky diode may be used in applications where bemf voltage must be used for head parking. 28 v in input for motor current control voltage. 29 comp a capacitor and resistor are connected to this pin for external compensation of the transconductance loop. 30 slew input for connection of a resistor for configuration of the output slew rate during commutation. 35, 36, 37, 58, 59 sense pin for connection of rsense, an external resistor used to sense the motor current 38 cboost pin for connection of capacitor to ground for the internal step up converter. 43 lboost pin for connection of inductor to v dd for the internal step up converter. 51 pd_cap external capacitor to ground which stores energy for use during braking. 52 brk active low logic input that turns off all drivers, and triggers the delayed brake. 53 brk_dly pin for connection of external rc network to configure delay of braking. 60 gain logic input to configure the gain in the current sense feedback loop (k). low state produces gain of 4, high state produces a gain of 16. 61 clock rising edge triggered input used to increment the commutation sequencer. 62 reset logic input used in conjunction with clock. for clock = low and reset = high the sequencer is forced to state 1. for clock = high and reset = high an immediate brake is initiated. an immediate brake implies no delay. L6237 3/11
electrical characteristics (v p = 5v; tamb = 25 c; unless otherwise specified.) symbol parameter test condition min. typ. max. unit v p power supply voltage 4.5 5 5.5 v i p supply current drivers off brake = high brake = low 8 1 ma ma i dsx output leakage current 1 ma r ds(on) sink output on resistance t j = 125 c 0.75 w source output on resistance 0.75 w v ds(sat) source saturation voltage i ds =1a t j = 125 c 0.75 v sink saturation voltage 0.75 v v f body diode forward drop i ds = 1a 1.3 v t prk maximum brake delay time brk 0v or v p 0v; c pdcap = 4.7 m f; r dson 4 w 0.3 s t brk maximum brake time 4 s i er error amplifier input bias current 1 m a v ear error amp. input linear range 0 4 v k sense amplifier gain gain = low gain = high 4 16 v/v sense amp. input bias current 1 m a v sar sense amp. input linear range gain = low gain = high 0 0 1 0.25 v v v clo current loop total offset voltage tbd mv v inh logic input voltage 2 v v inl 0.8 v i inh logic input current v in =5v 1 m a i inl v in =0v 1 m a t don1 upper/lower turn-on delay upper tbd m s t don2 lower tbd m s t doff1 upper/lower turn-off delay upper tbd m s t doff2 lower tbd m s t sd shutdown temperature 160 c t sdr recovery temperature 120 c c boost step-up converter storage capacitor 1 m f l boost step-up converter charging inductor 220 m h dv/dt dmos output turn-off slew rate r slew = 100k 150 mv/ m s i omax bemf output source/sink current v drop = 0.4v 0.36 ma t inc min. clock pulse width to increment sequencer v dd = 5v 500 ns f clk max. sequencer clock frequency (50% d.c.) v dd = 5v 1 mhz r ct value of oyo connected center tap resistors 20 k w f ref max. fref clock frequency (50% d.c.) v dd = 5v 10 mhz L6237 4/11
spindle drive functional description the commutation is accomplished via three logic inputs (clock, reset, mux_sgl). a positive transition at the clock input will increment the in- ternal sequencer producing commutation to the next phase (refer to logic truth table for explana- tion of sequencer operations). the L6237 performs internal sensing of the back electromotive force (bemf), giving a cmos compatible logic output signal that is high or low if the current bemf voltage is respectively above or below the central tap voltage. for application in which the center tap is not connectable to the relative input pin, three resistors are internally available from outputs in a oyo configuration to simulate the presence of the center tap. the bemf comparator input is internally switched to the output phase that is in tristate condition, while the output is selectable via the mux_sgl input. when mux mode is selected the bemf output will track the current floating phase, as deter- mined by the sequencer state. when sgl mode is active, only the c output bemf is provided. the L6237 performs an adaptive digital mask to block unwanted zero crossing generated during phases commutation. this mask is activated when a positive clock transition increments the sequencer, and remains active for a period that is one fourth of the period between two zero cross- ing. considering that a full increment of the se- quencer (one oelectricalo revolution) gives 6 differ- ent output states, the period between two commutation can be considered of 60 electrical degrees, so that the masking time is 15 electrical degrees. an input clock signal fref is requireed as a time base for the internal mask counters. the brk and brk_dly inputs offer flexibility to the system designer in the implementation of the braking function. the brk input, when pulled low, turns off all upper and lower dmos drivers. this figure 1: sequencer timing diagram. sequencer states sequencer truth table outa outb outc clk reset mux_sgl operating mode state1 i+ i- 0 x 0 0 single bemf drivers enabled state2 i+ 0 i- x 0 1 mux bemf state3 0 i+ i- 0 1 0 initialize sequencer state4 i- i+ 0 x 1 1 tri-state, mux bemf state5 i- 0 i+ 1 1 0 logic brake, initialize seq. state6 0 i- i+ x = don't care indicates not level sensitive, increments sequencer on positive edge logic brk (seq->state1) i- i- i- i+: upper on, i-: lower on, 0: tri-state L6237 5/11
way the outputs are in tristate condition, and since no brake is applied to the motor, it will con- tinue its rotation, giving a bemf voltage propor- tional to its speed. the low transition at brk input will also produce a delayed negative transition at the brk_dly input. this delay is configurable by connecting a capacitor and resistor from the brk_dly pin to ground. the negative transition at this pin will initiate the braking of the motor by turning on all lower dmos, keeping all upper dmos turned off. this feature provides a time in- terval where the motor acts as a generator, whose bemf can be used to power the read/write parking function. as soon as the head has been parked, the motor can be really braked, stopping its rotation in a very short time. the brake function utilizes the energy stored in an ex- ternal capacitor to turn on or off the dmos pow- ers. this allows the braking procedure even if the vp supply has been powered down. additionally, while in brake mode, part of the analog circuitry is turned off and the quiescent current is minimized. this is useful in battery operated sistems when disk access is minimal. an immediate brake can be realized by simultaneously driving reset and clock high, and mux_sgl low. this will turn off the upper drivers turning on the lower drivers. braking occurs regardless of the condition of the brk_dly input. motor current is determined by a voltage imposed on the vin input. the sense pins are intended for connection of a resistor in series with the source of all lower dmos. the voltage at this pin provides the feedback signal which is utilized in- ternally to regulate the motor current. this one can be determined by the expression imotor = vin/k*rsense where k is the voltage gain of the sense amplifier. a value of 4 or 16 is selectable by the gain logic input. the current is regulated by a linear transconductance loop which drives the lower dmos. the control is passed to each lower dmos in succession during the commuta- tion sequence. to avoid recirculation of the current flowing in the coils of the motor when each phase is commu- tated, the turn off slew rate of the upper an lower drivers is externally configurable using a single resitor. this defines a current that is internally used to discharge a capacitor. the profile of the voltage across this capacitor will be reproduced at the output, performing the slew rate control. be- cause of this control the current flowing in the switched off coil will decrease to zero with a quadratic slope, while the total current in the mo- tor is kept constant by the transconductance loop. thermal protection circuitry will shut off all drivers when the chip junction temperature exceeds the threshold temperature. a small amount of hyster- esis is included to prevent rapid on/off cycling of the power stages. circuit operation and formulas brake delay the amount of time that a signal transition takes to propagate from brk to brk_dly pins can be determined by the espression td @ 1.5 ? rc [ms] where r and c are the values of the resistor an capacitor connected to brk_dly pin. with the above expression the value of td is expressed in milliseconds. transconductance loop gain the transconductance is given by the expression: gm = 1/(k ? rsense) where k can be 4 or 16 depending on the state of pin gain. if gain=0, k=4; if gain=1, k=16. as a result the total current flowing in the motor is: im = gm ? vin = vin/(k ? rsense) where vin is the voltage applied to pin v in . slew rate control by means of an external resistor it is possible to configure the turn off slew rate following this ex- pression: sr = 15/rslew(k w )[v/ m s] rslew is the resistor connected to pin slew and its value is espressed in kohms, while the sr value will be v/ m s. digital bemf masking: theory of op- eration a 9 bit up counter is used to measure the period between to successive zero crossings. this ope- riod countero counts a frequency that is fref/2e6 = fref/64. when a new zero crossing is detected, the period counter will transfer its contents to the 6 bit down counter that is the real omask countero. the up counter will then reset to zero and com- mence the counting of the following period. since that the mask counter uses a frequency that is fref/2e7 = fref/128, that is half of the fre- quency used by the up counter, the final masking time will be one fourth of the period between to successive zero crossings or, in other terms, 15 electrical degrees. during start up, when the period is quite large, the period counter will saturate when all bit are in o1o state, providing a maximum mask interval. as the motor speed increases, a fixed masking time will be applied until the period between two commuta- tions is less than the maximum time of the period counter. this means that the masking time will be propor- tional for commutations period that are less than L6237 6/11
2e9/(fref/64). there are three parameters that are affected by the choice of fref: 1)maximum masking time, tmax, that can be calculated as: tmax = 2e6/(fref/128) = 2e13/fref 2)minimum time resolution of the mask counter, that is 1 bit or: tres = 128/fref 3)truncation error, et, coming from the appros- simation caused by the division by 4, that will typically generate non integer numbers, whose decimals will be skipped. this error is again one bit (with the period of the frequency used by the down counter) or: et = 128/fref as a result of the above the maximum error of the masking time can be up to: emax = tres + et = 256/fref please note that the truncation error is not fixed, but depends from the period count and can also be null if the count between two zero crossings can be exactly divided by 4. as an example, we can consider the case of an 8pole, three phases motor rotating at 5400 rpm. let consider fref = 8mhz. 8 poles 4 electrical cycles for each mechani- cal revolution and 3 phases 6 commutations for each electrical cycle therefore: commutation frequency = 5400 rev/min * 1min/60seconds * 24comm/rev = 2160hz. this means that the commutation period is about 463 microseconds. considering the above ex- pression we will have: tmax = 2e13/8e6 = 1.024ms this means that the masking time will be propor- tional starting from a commutation period lower than 4tmax = 4.096ms that means a speed higher than 610 rpm. additionally we will have: tres = 128/fref = 16 m s emax = 256/fref = 32 m s with a commutation period of 463 microseconds, we should have a masking time of 463/4 = 116 m s so that we obtain: accuracy = 32/116 = 27.6% this is the maximum error. considering the real situation and mainly the real truncation error we will have in this particular situation an emax=20 microseconds so that the accuracy is about 17.3% application information a typical application configuration of the L6237 driving a three phase brushless sensorless dc motor is shown in fig.6. the spindle motor typically is a 2.5o rigid disk driver having 1.3 w - 0.1mh per phase, star con- nected. this kind of load requires a suitable compensa- tion of the linear control loop that can be achieved by an rc network of 10k and 10nf, connected to the ocompo pin. changing the motor characteristics, the rc net- work could be modified for the best performances of the system. this is a suggestion about how to choose the value of the rc compensation network of the cur- rent loop: the following figure shows the entire control system of the current regulator. the error amplifier is a transconductance ampli- fier. it is used in open loop configuration inside the main control loop and its gain and frequency figure 2: typical normalized r ds (on) vs. junction temperature. figure 3: typical transient thermal impedance vs. time or pulse width single pulse L6237 7/11
response are determined by a compensation net- work connected between its output and ground. this ota has a large bandwidth (300khz) and so its pole does not interfere with the pole and zero of the motor + power mos system and of the compensation network. in the application the rc network gives an high system gain at low fre- quency to ensure good precision and a low gain at high frequency to ensure stability of the sys- tem. the figure 5 shows the bode plot of the com- pensated error amplifier plus power stage and motor. the rc value of the compensating network must be choosen to have for high frequencies a flat gain of about 20db so that the double pole of the motor makes the bode diagram change its slope and decrease with 40db/decade stabilizing the whole system cutting the bandwidth. an empiric way to find good rc value for compensation net- work can be the follow: 1)set a great value of c in order to not interfere at high frequencies 2)give, with motor completely stopped, an exci- tation as voltage step and act on r in order to get an acceptable current overshoot 3)decrease the value of c until to have a good gain at low frequencies. to drive the upper dmos a voltage higher than the power supply vp is needed. the step-up inte- grated in the L6237 keeps the cboost storage capacitor at the correct voltage. the switching of the internal step-up circuit can create some noise that could disturb the current control loop. in order to minimize the interference between the step-up circuit and the linear control loop of the output current is suggested to choose an lboost of 220 m h with an equivalent series resistor minimum of 2 w . another way to decoupling the noise effects of the step-up from the linear control loop is taking care in the pc board design about the ground path. the charging current of the inductor, for the inter- nal step-up converter, flowing through the pin lboost (43) is coming out from the device at gnd pin 42. a good solution is to keep separate in the pc board the gnd track connection of this pin (42) from the other gnd pins (6,7,8,40,41). pin 37 of the device is the input of the internal sense amplifier (see fig. 4). the voltage at this pin provides the feedback sig- nal which is internally used to regulate the mo- torurrent. in order to have no differences in regulated cur- figure 4. figure 5. L6237 8/11
rent level of the three phase currents, is sug- gested to connect the sense resistor using two differents tracks: one for the connection of the sources of the output dmos (pins 35, 36, 58, 59) and another one for the sense amplifier input (pin 37). the typical application of the L6237 is in hdd systems where there is the need to park the read-write heads before the motor braking. at power supply switch-off the brk input is driven low (active low), so the power output stage is switched in a high impedance state. the schottky diode 1n5818 insulates the L6237 from the main power supply. the spindle motor now, acting as a three-phase alternator, supplies the heads voice- coil motor through integrated diodes that rectifie the emfvoltage. after a delay longer than the parking time, the lower output dmos can be switched-on and the spindle motor is braked. figure 6: application circuits L6237 9/11
a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b pqfp64 l l1 seating plane 0.10mm tqfp64 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.85 0.073 a1 0.25 0.010 a2 1.30 1.40 1.50 0.051 0.055 0.059 b 0.18 0.23 0.28 0.007 0.009 0.011 c 0.12 0.16 0.20 0.0047 0.0063 0.0079 d 12.60 0.496 d1 10.00 0.394 d3 7.50 0.295 e 0.50 0.0197 e 12.60 0.496 e1 10.00 0.394 e3 7.50 0.295 l 0.40 0.50 0.60 0.0157 0.0197 0.0236 l1 1.30 0.052 k 0 (min.), 5 (max.) L6237 10/11
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications men- tioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. L6237 11/11

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